1. Field of the Invention
The present invention relates to a high speed ROM (Read Only Memory)-based Nyquist FIR (Finite Impulse Response) filter, and in particular, to an improved high speed ROM-based Nyquist FIR filter which is capable of enhancing a modulation speed without increasing an operational frequency of a filter by increasing the number of output signals from each ROM by providing two ROMs each having a predetermined size which is half the size of a conventional ROM, differently from a conventional filter-based method which uses one ROM.
2. Description of the Conventional Art
Generally, the digital modulation Nyquist FIR filter is a FIR filter having a T-tap 1:N interpolation ratio and creates a N-number of filter output signals. Therefore, the operational frequency of the filter becomes N-time of the input data speed. In the case of the broadband digital communication, since the input data speed is greatly increased as a band is expanded, a filter is configured such that a high speed modulation is obtained. The conventional filter construction for a high speed processing mainly uses a transversal structure method. However, this method has a disadvantage in that many circuits are used. In order to overcome the above-described problem, a filter using a ROM is used for reducing the number of circuits and enabling a high speed processing. Therefore, it is possible to reduce the size of the ROM by using the characteristic of the filter. A method is disclosed to reduce the size of the ROM using the characteristic of the filter from Nx2.sup.T/N to Nx2.sup.T/2N-1. As shown in FIG. 1, the above-described method is directed to a circuit of a 48-tap 1:4 interpolation FIR filter (T=48, N=4). The basic principle used in the conventional art may be expressed as the following mathematic equation (matrix) 1 of the filter. In the final matrix shown in the mathematic equation 1, the filter coefficients C(24), . . . , C(47) are substituted with C(23), . . . , C(0) using a symmetric characteristic of the filter coefficient of C(k) =C(47-k), and each row of the second coefficient matrix and a data vector is formed in the reverse order, and the matrix is formed using a characteristic that D(m)=.+-.1 of an NRZ (Non-Return-to-Zero) signal.
[Mathematic Equation (Matrix) 1] ##EQU1## where, C(k)=C(47-k) and D(m)=.+-.1
Since the second coefficient matrix of the mathematic equation 1 is identical to the first row except the order of the row, it is known that it is possible to compute the output of the filter based on the mathematic equation 1 using one ROM storing all results of the first coefficient matrix. Since the number of data which is multiplied by the coefficient matrix is 5, a ROM block is needed for storing the results of 2.sup.5 for each row computation. Therefore, the size of the entire ROM is 4.times.2.sup.5 (=Nx2.sup.T/2N-1 if T=48, N=4). This means that the size of the entire ROM is relatively small compared with the size (4.times.2.sup.2) of the ROM used for the filter based on a conventional ROM.
The circuits shown in FIG. 1 will be explained in more detail with reference to the mathematic equation 1. First, 12 channel data are shifted at a predetermined interval in the first and second shift registers 10 and 11 of two 6-bit which are connected in series. A multiplexer 20 selects a 6-bit data stored in the first shift register 10 when a selection signal line is 0 and selects data stored in the second shift register 11 when a selection signal line is 1 in the reverse order, respectively. The reason for selection in the reverse order is that the data with respect to the second coefficient matrix of the mathematic equation 1 should be inputted in the reverse order. 5-bit data except the most significant bit (MSB) among the 6-bit selected data form a lower address of the ROM 30. An XOR gate group 50 is used for inverting the lower address of the ROM when the most significant bit is 1. Namely, this corresponds to D(m).times.D(m-k) in the data vector of the mathematic equation 1. The upper address 2-bit (=log(N=4)) of the ROM 30 is generated by the XOR gate group 70. The thusly generated upper address is used for selecting an internal block of the ROM storing the internal result with respect to each row of the coefficient matrix. The order of the selection is (0,3), (1,2), (2,1), (3,0). In addition, the order thereof is expressed in the binary digits as follows: (00, 11), (01, 10), (10, 01), (11, 00). The inverted signal is generated by the selection signal line of the multiplexer 20. Therefore, when the selection signal line is 0, the internal result with respect to the (k)th ROM block is read from the ROM 30 with respect to the data from the first shift register 10 and is stored into the intermediate register 80. The internal result with respect to the (3-k)th row and the intermediate result stored in the register 80 are added with respect to the data which is obtained by changing the selection signal line to 1, for thus outputting one output value. The above-described steps are repeated by a predetermined number corresponding to the result of four interpolations, and the input shift register is shifted by one (1) bit. The XOR gate group 60 operates to invert the output signal from the ROM when the most significant bit selected by the multiplexer 20 is 1. Namely, the above-described operation is performed identically to an operation that 1's complement is obtained with respect to the internal result. Namely, since 1 is added by the input carry of the adder 40, 2's complement is obtained. In FIG. 1, it is possible to implement a small size circuit by reducing the number of ROMs used. However, in order to compute one filter output, the ROM should be read twice, so that the processing speed is reduced by 1/2 compared to the conventional ROM-based filter circuit. In addition, the delay time which is required for the entire circuit including the delay time for the adder is significantly increased. Therefore, when increasing the operational frequency of the filter for a high speed processing, the hardware is expensive since the high performance ROM and adder should be used in order to reduce the delay time of the ROM and adder.